256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Figure 21: READ followed by WRITE: BL = 2; RL = 5; WL = 2
0
1
2
3
4
5
6
7
8
9
CK#
CK
CMD
RD
NOP
NOP
NOP
NOP
WR
WR
NOP
NOP
NOP
ADDR
A
BA0
RL = 5
A
A
BA1
BA2
WL = 2
DQ
Q0a Q0b
D1a D1b D2a D2b
DVLD
DQSx
DQSx#
DON’T CARE
Figure 22: READ followed by WRITE: BL = 2; RL = 5; WL = 2 – Interleaved Data
0
1
2
3
4
5
6
7
8
CK#
CK
CMD
RD
WR
NOP
NOP
NOP
WR
NOP
NOP
NOP
UNDEFINED
9
NOP
ADDR
A
BA0
A
BA1
RL = 5
WL = 2
A
BA2
WL = 2
DQ
DVLD
DQSx
DQSx#
D1a D1b
Note:
A/BAx: address A of bank x
Dxy: data y to bank x
RD: READ
RL: READ latency
WL: WRITE latency.
Q0a Q0b
D2a D2b
DON’T CARE
UNDEFINED
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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©2001 Micron Technology, Inc. All rights reserved.