256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Figure 19: READ Burst: BL = 2; RL = 5
0
1
2
3
4
5
6
7
8
CK#
CK
CMD
RD
RD
RD
RD
RD
RD
RD
RD
RD
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA7
A
BA6
A
BA5
A
BA0
RL = 5
DQSx
DQSx#
DVLD
DQ
Q0a Q0b Q1a Q1b Q2a Q2b Q3a
DON’T CARE
UNDEFINED
Figure 20: READ Burst: BL = 4; RL = 5
0
1
2
3
4
5
6
7
8
CK#
CK
CMD
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDR
A
BA0
A
BA2
A
BA4
A
BA6
A
BA1
RL = 5
DQSx
DQSx#
DVLD
DQ
Q0a Q0b Q0c Q0d Q2a Q2b Q2c
Note:
A/BAx: address A of bank x
Dxy: data y to bank x
RC: row cycle time
RL: READ latency.
DON’T CARE
UNDEFINED
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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©2001 Micron Technology, Inc. All rights reserved.