MT49H16M16 View Datasheet(PDF) - Micron Technology

Part Name

Description

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MT49H16M16

REDUCED LATENCY DRAM (RLDRAM®)

Micron Technology 

256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM

Commands

Table 7: Description of Commands

Command

DESEL/NOP1

MRS

READ

WRITE

AREF

Description

The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects

the chip. Use the NOP command to prevent unwanted commands from being registered during idle

or wait states. Operations already in progress are not affected. Output values depend on command

history.

The mode register is set via the address inputs A(17:0). See Figure 9 on page 15 for further

information. The MRS command can only be issued when all banks are idle and no bursts are in

progress.

The READ command is used to initiate a burst read access to a bank. The value on the BA(2:0) inputs

selects the bank, and the address provided on inputs A(19:0) selects the data location within the

bank.

The WRITE command is used to initiate a burst write access to a bank. The value on the BA(2:0)

inputs selects the bank, and the address provided on inputs A(19:0) selects the data location within

the bank. Input data appearing on the DQs is written to the memory array subject to the DMx input

logic level appearing coincident with the WRITE command. If the DM0 signal is registered LOW, the

first half of the burst WRITE data will be written to memory, if registered HIGH, the corresponding

data inputs will be ignored (i.e., this part of the data word will not be written). If the DM1 signal is

registered LOW, the second half of the burst WRITE data will be written to memory, if registered

HIGH, the corresponding data inputs will be ignored (i.e., this part of the data word will not be

written).

The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank.

The command is nonpersistent, so it must be issued each time a refresh is required. The value on the

BA(2:0) inputs selects the bank. The refresh address is generated by an internal refresh controller,

effectively making each address bit a “Don’t Care” during the AREF command. The RLDRAM

requires 64K cycles at an average periodic interval of 0.49µs 2(MAX). To improve efficiency, eight

AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 3.9µs.3

Notes: 1. When the chip is deselected, internal NOP commands are generated and no commands are

accepted.

2. Actual refresh is 32ms/8K/8 = 0.488µs.

3. Actual refresh is 32ms/8k = 3.90µs.

pdf: 09005aef81121545/source: 09005aef810c0ffc

256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001 Micron Technology, Inc. All rights reserved.

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