CK/CK#
CMD
WR0
DQ
DM0
DM1
WR DATA
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE DATA MASK TIMING
(BL = 2, WL = 2)
WR1
WR2
WR3
WR4
D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b
tAS
D0a D0b
tAH
D1b D2a
D4a D4b
NOTE: 1. Shaded WR Data is not written into the memory.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
32
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©2002, Micron Technology, Inc.