ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
EXAMPLE OF REFRESH IMPLEMENTATION
(Cyclic Bank Burst Refresh)
CLK/CLK#
CMD/ADR RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7
3.9µs
RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7
NOTE: 1. Cyclic Burst refresh on all Banks.
2. Each Refresh command on the next Bank is asserted on the next clock rising edge.
3. Cycle for a burst refresh: 32ms/8192 = 3.9µs.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
31
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