1
CK/CK#
CS#, AS#, REF#,
A[18:0], BA[2:0],
DM[1:0]
WB0
DQ
ADVANCE
256Mb: x16, x32
2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
WRITE TIMING
(BL = 4, RL = 6)
2
3
4
5
6
7
8
9
WB1
WB2
tRC = 8 tCK
WB3
WB0
D0a D0b D0c D0d D1a D1b D1c D1d D2a D2b D2c D2d D3a D3b D3c D3d
NOTE: 1. DQS and DQS# are not relevant during WRITE cycles.
2. Starting with all banks closed, 4 banks cyclic access.
3. Write latency WL = RL - BL/2 - 2 = 2.
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
27
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©2002, Micron Technology, Inc.