74ACTQ16543MTD View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

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74ACTQ16543MTD

16-Bit Registered Transceiver with 3-STATE Outputs

Fairchild Semiconductor 

Connection Diagram

Pin Assignment for SSOP and TSSOP

Functional Description

The ACTQ16543 contains sixteen non-inverting transceiv-

ers with 3-STATE outputs. The device is byte controlled

with each byte functioning identically, but independent of

the other. The control pins may be shorted together to

obtain full 16-bit operation. The following description

applies to each byte. For data flow from A to B, for exam-

ple, the A-to-B Enable (CEABn) input must be LOW in

order to enter data from A0–A15 or take data from B0–B15,

as indicated in the Data I/O Control Table. With CEABn

LOW, a LOW signal on the A-to-B Latch Enable (LEABn)

input makes the A-to-B latches transparent; a subsequent

LOW-to-HIGH transition of the LEABn signal puts the A

latches in the storage mode and their outputs no longer

change with the A inputs. With CEABn and OEABn both

LOW, the 3-STATE B output buffers are active and reflect

the data present at the output of the A latches. Control of

data flow from B to A is similar, but using the CEBAn,

LEBAn and OEBAn inputs.

Data I/O Control Table

CEABn

H

X

L

X

L

Inputs

LEABn

X

H

L

X

X

OEABn

X

X

X

H

L

Latch Status

(Byte n)

Latched

Latched

Transparent

—

—

Output

Buffers

(Byte n)

High Z

—

—

High Z

Driving

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

A-to-B data flow shown; B-to-A flow control

is the same, except using CEBAn, LEBAn and OEBAn

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