673M-01IT View Datasheet(PDF) - Integrated Device Technology

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673M-01IT

PLL BUILDING BLOCK

Integrated Device Technology 

ICS673-01

PLL BUILDING BLOCK

PLL BUILDING BLOCK

Determining the Loop Filter Values

The loop filter components consist of CS, CP, and RS.

Calculating these values is best illustrated by an example.

Using the example in Figure 1, we can synthesize 20 MHz

from a 200 kHz input.

The phase locked loop may be approximately described by

the following equations:

BandwidthNBW = R----S----⋅-----K----O----⋅-----I-C----P-

2πN

Damping factor,ζ=

R----S-

2

K----O-----⋅-----I--C---P----⋅------C----S-

N

where:

KO = VCO gain (Hz/V)

Icp = Charge pump current (A)

N = Total feedback divide from VCO,

including the internal VCO post divider

CS = Loop filter capacitor (Farads)

RS = Loop filter resistor (Ohms)

As a general rule, the bandwidth should be at least 20 times

less than the reference frequency, i.e.,

BW ≤(REFIN) ⁄ 20

In this example, using the above equation, bandwidth

should be less than or equal to 10 kHz. By setting the

bandwith to 10kHz and using the first equation, RS can be

determined since all other variables are known. In the

example of Figure 1, N = 200, comprising the divide by 2 on

the chip (VCO post divider) and the external divide by 100.

Therefore, the bandwidth equation becomes:

0,000 = R----S-----⋅-----1---9---0----⋅------1---0---6----⋅------2--.--5----⋅------1---0---–

2π ⋅ 200

and RS = 26 kΩ

Choosing a damping factor of 0.7 (a minimal damping factor

than can be used to ensure fast lock time), damping factor

equation becomes:

and CS = 1.32 nF (1.2 nF is the nearest standard value).

The capacitor CP is used to damp transients from the

charge pump and should be approximately 1/20th the size

of CS, i.e.,

CP ≅ CS ⁄ 20

Therefore, CP = 60 pF (56 pF nearest standard value).

To summarize, the loop filter components are:

CS = 1.2 nf

CP = 56 pf

RS = 26 kΩ

Output Clock Alignment to REFIN

When choosing either CLK1 or CLK2 to drive the feedback

divider, ICS recommends that CLK2 be used so that the

falling edges of CLK2 and REFIN, and the rising edge of

CLK1, are all synchronized. If CLK1 is used for feedback,

CLK2 may be either a rising or falling edge when compared

to REFIN. See diagrams below.

CLK1

CLK2

REFIN

CLK2 Feedback

CLK1

CLK2

REFIN

CLK1 Feedback

0.7

=

-2--5---,---0--0---0-

2

1---9---0----⋅------1---0---6----⋅------2---.-5----⋅------1---0---–--6----⋅------C----S-

200

IDT™ / ICS™ PLL BUILDING BLOCK

7

ICS673-01 REV Q 071906

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