datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

673M-01LF View Datasheet(PDF) - Integrated Device Technology

Part Name
Description
View to exact match
673M-01LF
IDT
Integrated Device Technology IDT
673M-01LF Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
ICS673-01
PLL BUILDING BLOCK
PLL BUILDING BLOCK
CHGP VCOIN
CAP PD
CP
R2
RS
CS
-
+
R3
R4
Figure 2. Using an External Comparator
to Reset the VCO
The CLK output frequency may be up to 2x the maximum
Output Clock Frequency listed in the AC Electrical
Characteristics above when the device is in an unlocked
condition. Make sure that the external divider can operate
up to this frequency.
Explanation of Operation
The ICS673-01 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The device
uses external PLL loop filter components which through
proper configuration allow for low input clock reference
frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling edges of
the clocks inputted to FBIN and REFIN. It then generates an
error signal to the charge pump, which produces a charge
proportional to this error. The external loop filter integrates
this charge, producing a voltage that then controls the
frequency of the VCO. This process continues until the
edges of FBIN are aligned with the edges of the REFIN
clock, at which point the output frequency will be locked to
the input frequency.
Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.
0.01 F
200 kHz
+3.3 or 5 V
CP
RS CS
SEL OE PD VDD CHGP VCOIN
CAP
REFIN
FBIN
ICS673-01
CLK1
CLK2
GND
40 MHz
20 MHz
200 kHz
100
Digital Divider
such as ICS674-01
IDT™ / ICS™ PLL BUILDING BLOCK
6
ICS673-01 REV Q 071906
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]