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MAX3946_10 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3946_10 1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MaximIC
Maxim Integrated MaximIC
MAX3946_10 Datasheet PDF : 28 Pages
First Prev 21 22 23 24 25 26 27 28
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Table 6. Register Summary (continued)
REGISTER
FUNCTION/
ADDRESS
REGISTER
NAME
NORMAL
MODE
SETUP
MODE
BIT
NUMBER/
TYPE
BIT NAME
DEFAULT
VALUE
NOTES
R
R
Modulation
Current
RW
RW
Increment
Setting Register
MODINC
RW
RW
Address =
RW
RW
H0x0C
RW
RW
RW
RW
R
R
Bias Current
Increment
RW
RW
Setting Register BIASINC
RW
RW
Address =
H0x0D
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Mode Control
RW
RW
Register
Address =
RW
RW
MODECTRL
RW
RW
H0x0E
RW
RW
RW
RW
RW
RW
Pulse-Width
R
RW
Control Register
SET_
R
RW
Address =
PWCTRL
R
RW
H0x0F
R
RW
R
RW
R
RW
Deemphasis
R
RW
Control Register SET_TXDE
Address = H0x10
R
RW
R
RW
R
RW
Equalization
R
RW
Control Register SET_TXEQ
Address = H0x11
R
RW
7
SET_IMOD[0]
0
LSB of SET_IMOD DAC
register address = H0x09
4
MODINC[4]
0
MSB MOD DAC two’s
complement
3
MODINC[3]
0
2
MODINC[2]
0
1
MODINC[1]
0
0
MODINC[0]
0
LSB MOD DAC two’s
complement
7
SET_IBIAS[0]
0
LSB of SET_IBIAS DAC
register address = H0x08
4
BIASINC[4]
0
MSB bias DAC two’s
complement
3
BIASINC[3]
0
2
BIASINC[2]
0
1
BIASINC[1]
0
0
BIASINC[0]
0
LSB bias DAC two’s
complement
7
MODECTRL[7]
0
MSB mode control
6
MODECTRL[6]
0
5
MODECTRL[5]
0
4
MODECTRL[4]
0
3
MODECTRL[3]
0
2
MODECTRL[2]
0
1
MODECTRL[1]
0
0
MODECTRL[0]
0
LSB mode control
3
SET_PWCTRL[3]
0
MSB Tx pulse-width
control
2
SET_PWCTRL[2]
0
1
SET_PWCTRL[1]
0
0
SET_PWCTRL[0]
0
LSB Tx pulse-width con-
trol
5
SET_TXDE[5]
0
MSB Tx deemphasis
4
SET_TXDE[4]
0
3
SET_TXDE[3]
0
2
SET_TXDE[2]
0
1
SET_TXDE[1]
0
0
SET_TXDE[0]
1
LSB Tx deemphasis
2
SET_TXEQ[2]
0
Tx equalization
1
SET_TXEQ[1]
0
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