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MAX3946_10 データシートの表示(PDF) - Maxim Integrated

部品番号コンポーネント説明メーカー
MAX3946_10 1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance MaximIC
Maxim Integrated MaximIC
MAX3946_10 Datasheet PDF : 28 Pages
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1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Bit #
7
6
Name
SET_IBIAS
[0] (LSB)
X
Default Value
0
0
Bias Current Increment Setting Register (BIASINC)
5
4
3
2
1
0
ADDRESS
X
BIASINC BIASINC BIASINC BIASINC BIASINC
[4] (MSB)
[3]
[2]
[1]
[0] (LSB)
H0x0D
0
0
0
0
0
0
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0].
Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the
SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two’s complement string.
Bit #
Name
Default Value
Mode Control Register (MODECTRL)
7
6
5
4
3
2
1
0
ADDRESS
MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL
[7] (MSB)
[6]
[5]
[4]
[3]
[2]
[1]
[0](LSB)
0
0
0
0
0
0
0
0
H0x0E
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables the user to switch between normal and setup modes.
The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write opera-
tion. Exceptions are MODINC and BIASINC, which can be updated in normal mode.
Pulse-Width Control Register (SET_PWCTRL)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
SET_PWCTRL SET_PWCTRL SET_PWCTRL SET_PWCTRL
X
X
X
X
[3] (MSB)
[2]
[1]
[0] (LSB)
H0x0F
Default Value
X
X
X
X
0
0
0
0
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width.
Bit #
7
Name
X
Default Value
X
Deemphasis Control Register (SET_TXDE)
6
5
4
3
2
1
0
ADDRESS
SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE
X
[5] (MSB)
[4]
[3]
[2]
[1]
[0] (LSB) H0x10
X
0
0
0
0
0
1
Bits 5 to 0: SET_TXDE[5:0]. This is a 6-bit register used to control the amount of deemphasis on the transmitter output.
When calculating the total modulation current, the amount of deemphasis must be taken into account. The deemphasis
is set as a percentage of modulation current.
Equalization Control Register (SET_TXEQ)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
Name
X
X
X
X
X
SET_TXEQ SET_TXEQ
X
[2]
[1]
H0x11
Default Value
X
X
X
X
X
0
0
X
Bits 2 to 1: SET_TXEQ[2:1]. These 2 bits are used to control the amount of equalization on the transmitter input. See
Table 1 for more information.
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