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74VCX16827MEAX View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
74VCX16827MEAX Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs Fairchild
Fairchild Semiconductor Fairchild
74VCX16827MEAX Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
March 1998
Revised April 1999
74VCX16827
Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant
Inputs and Outputs
General Description
The VCX16827 contains twenty non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver carrying parity. The device is byte controlled. Each
byte has NOR output enables for maximum control flexibil-
ity.
The 74VCX16827 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
2.5 ns max for 3.0V to 3.6V VCC
3.0 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16827MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I19
O0–O19
Description
Output Enable Input (Active LOW)
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS500131.prf
www.fairchildsemi.com
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