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74ACT573SC View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74ACT573SC
Fairchild
Fairchild Semiconductor Fairchild
74ACT573SC Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Truth Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
Outputs
On
H
L
O0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of
Latch Enable
Functional Description
The 74AC573 and 74ACT573 contain eight D-type
latches with 3-STATE output buffers. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters
the latches. In this condition the latches are transparent,
i.e., a latch output will change state each time its D-type
input changes. When LE is LOW the latches store the
information that was present on the D-type inputs a
setup time preceding the HIGH-to-LOW transition of LE.
The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.5
2
www.fairchildsemi.com
 

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