DP80390 View Datasheet(PDF) - Digital Core Design
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DP80390 Datasheet PDF : 10 Pages
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Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK peri-
ods when appropriate timer is enabled. In the
counter mode the timer registers are incre-
mented every falling transition on their corre-
sponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock source for UARTs.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) regis-
ters. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF0 loads the transmit register, and reading
SBUF0 reads a physically separate receive
register. Works in 3 asynchronous and 1 syn-
chronous modes. UART0 can be synchronized
by Timer 1.
Ports - Block contains 8051’s general purpose
I/O ports. Each of port’s pin can be read/write
as a single bit or as a 8-bit bus P0, P1, P2, P3.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Man-
agement Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hard-
ware debugger provides debugging capability
of a whole SoC system. In contrast to other on-
chip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
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registers, internal, external, program memo-
ries, all SFRs including user defined peripher-
als. Hardware breakpoints can be set and con-
trolled on program memory, internal and exter-
nal data memories, as well as on SFRs. Hard-
ware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. Two additional pins
CODERUN, DEBUGACS indicate the sate of
the debugger and CPU. CODERUN is active
when CPU is executing an instruction. DE-
BUGACS pin is active when any access is per-
formed by DoCD™ debugger. The DoCD™
system includes JTAG interface and complete
set of tools to communicate and work with core
in real time debugging. It is built as scalable
unit and some features can be turned off to
save silicon and reduce power consumption. A
special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when de-
bug option is no longer used.
PROGRAM CODE SPACE
IMPLEMENTATION
The figure below shows an example Pro-
gram Memory space implementation in sys-
tems with DP80390 Microcontroller core. The
On-chip Program Memory located in address
space between 0kB and 1kB is typically used
for BOOT code with system initialization func-
tions. This part of the code is typically imple-
mented as ROM. The On-chip Program Mem-
ory located in address space between 60kB
and 64kB is typically used for timing critical
part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
a top performance up to 200 million instruc-
tions per second (many instructions executed
in one clock cycle). The off-chip Program
Memory located in address space between
1kB and 60kB, and above 64 kB is typically
used for main code and constants. This part of
the code is usually implemented as ROM,
SRAM or FLASH device. Because of relatively
long access time the program code executed
from mentioned above devices must be
fetched with additional Wait-States. Number of
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