datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

DP80390 View Datasheet(PDF) - Digital Core Design

Part Name
Description
View to exact match
DP80390 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
SYMBOL
BLOCK DIAGRAM
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
prgromdata(7:0)
prgramdata(7:0)
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
sxdmxdatai(7:0)
ramdatai(7:0)
sfrdatai(7:0)
int0
int1
t0
t1
gate0
gate1
rxdi
tdi
tck
tms
reset
clk
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
sxdmadd(15:0)
sxdmdatao(7:0)
sxdmwe
sxdmoe
ramaddr(7:0)
ramdtao(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
rxdo
txd
tdo
rtck
coderun
debugacs
rsto
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
Opcode
decoder
Program
memory
interface
External
memory
interface
iprgromsize(2:0)
iprgramsize(2:0)
Control
Unit
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
Internal data
memory
interface
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
User SFR’s
interface
clk
reset
rsto
I/O Port
registers
Timers
UART
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
t0
t1
gate0
gate1
rxdi
rxdo
txd
Interrupt
controller
int0
int1
Power
Manage-
ment Unit
DoCD™
Debug Unit
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ALU
SXDM
interface
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
reset
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
iprgramsize[2:0]
iprgromsize[2:0]
prgramdata[7:0]
prgromdata[7:0]
sxdmdatai[7:0]
xdatai[7:0]
input
input
input
input
input
input
input
input
input
input
input
input
Global clock
Global reset
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Size of on-chip RAM CODE
Size of on-chip ROM CODE
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from sync external data
memory (SXDM)
Data bus from external memories
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]