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PIC18F65J50_09 View Datasheet(PDF) - Microchip Technology

Part NameDescriptionManufacturer
PIC18F65J50_09 PIC18F87J50 Family Silicon Errata and Data Sheet Clarification Microchip
Microchip Technology Microchip
PIC18F65J50_09 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIC18F87J50 FAMILY
4. Module: MSSP
With MSSP1 or MSSP2 in SPI Master mode, the
FOSC/64 or Timer2/2 clock rate enabled and
CKE = 0, a write collision may occur if SSPBUF is
loaded immediately after the transfer is complete.
A delay may be required before writing SSPBUF,
after the MSSP Interrupt Flag bit (SSPIF) is set or
the Buffer Full bit (BF) is set. If the delay is
insufficiently short, a write collision may occur as
indicated by the WCOL bit being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents.
Affected Silicon Revisions
A2 A3 A4
XXX
5. Module: I/O (PORTH)
When the Parallel Master Port (PMP) module is
enabled (PMCONH<7> = 1) and the PMPMX bit
is clear (CONFIG3L<2> = 0), the PMP module
can, under certain conditions, override firmware
control over the RH0 and RH1 general purpose
I/O (GPIO) pins.
The RH0 and RH1 pins will function normally
and can still be used as standard GPIO if the
PMP is disabled or the PMPMX Configuration bit
is set.
This issue only applies to the 80-pin devices
(PIC18F85J50, PIC18F86J50, PIC18F86J55
and PIC18F87J50).
Work around
None.
Affected Silicon Revisions
A2 A3 A4
XXX
DS80481A-page 4
© 2009 Microchip Technology Inc.
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