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PIC18F65J50_09 View Datasheet(PDF) - Microchip Technology

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Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
1. Module: MSSP (I2C™ Slave)
When configured for I2C™ slave reception, the
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I2C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPCON2<0>).
• Each time the SSPIF is set, read the SSPBUF
before the first rising clock edge of the next byte
being received.
Affected Silicon Revisions
A2 A3 A4
XXX
2. Module: MSSP (I2C™ Master)
When in I2C Master mode, if the slave performs
clock stretching, the first clock pulse after the slave
releases the SCL line may be narrower than the
configured clock width. This may result in the slave
missing the first clock in the next transmission/
reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Affected Silicon Revisions
A2 A3 A4
XXX
3. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled
(SPEN bit (RCSTAx<7>) = 0)
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
after enabling the module (setting SPEN,
CREN or TXEN = 1)
Work around
Add a 2 TCY delay after any instruction that re-
enables the EUSART module (ex: sets SPEN = 1).
See Example 1.
EXAMPLE 1: RE-ENABLING A EUSART MODULE
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2
nop ;1 Tcy delay
nop ;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
Affected Silicon Revisions
A2 A3 A4
XXX
© 2009 Microchip Technology Inc.
DS80481A-page 3
 

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