PIC18F65J50_09 View Datasheet(PDF) - Microchip Technology
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PIC18F65J50_09 Datasheet PDF : 16 Pages
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PIC18F87J50 FAMILY
8. Module: MSSP (SPI Master)
In Section 19.3.6, “Master Mode,” the following
content is added:
When used in Timer2 Output/2 mode, the SPI bit
rate can be configured using the PR2 Period
register and the Timer2 prescaler.
To operate in this mode, firmware must first
initialize and enable the Timer2 module before it
can be used with the MSSP. Once enabled, the
Timer2 module is free running and mostly
independent of the MSSP module.
Writing to the SSPxBUF register will not clear
the current TMR2 value in hardware. This can
result in an unpredictable SPI transmit MSb bit
width, depending on how close the TMR2 regis-
ter was to the PR2 match condition at the
moment that the firmware wrote to SSPxBUF.
To avoid the unpredictable MSb bit width, initial-
ize the TMR2 register to a known value when
writing to SSPxBUF. An example procedure,
which provides predictable bit widths (only
needed in the Timer2/2 mode), is given in
Example 2. The example procedure demon-
strates operation with MSSP1, but the concepts
apply equally to MSSP2.
EXAMPLE 2: LOADING SSPxBUF WITH THE TIMER2/2 CLOCK MODE
TransmitSPI:
BCF
PIR1, SSP1IF
MOVF
MOVWF
BCF
CLRF
MOVF
MOVWF
BSF
SSP1BUF, W
RXDATA
T2CON, TMR2ON
TMR2
TXDATA, W
SSP1BUF
T2CON, TMR2ON
;Make sure interrupt flag is clear (may have been set from previous
;transmission)
;Perform read, even if the data in SSPBUF is not important
;Save previously received byte in user RAM, if the data is meaningful
;Turn off timer when loading SSPBUF
;Set timer to a known state
;WREG = Contents of TXDATA (user data to send)
;Load data to send into transmit buffer
;Start timer to begin transmission
WaitComplete:
BTFSS PIR1, SSP1IF
BRA
WaitComplete
;Loop until data has finished transmitting
;Interrupt flag set when transmit is complete
9. Module: OSCTUNE Register
The second paragraph of Section 2.2.5.1
“OSCTUNE Register” is modified as indicated:
When the OSCTUNE register is modified, the
INTOSC frequency begins shifting to the new
value. The INTOSC clock stabilizes within 1 ms.
Code execution continues during this shift. There
is no indication that the shift has occurred.
DS80481A-page 12
© 2009 Microchip Technology Inc.
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