A29800ATV-55F View Datasheet(PDF) - AMIC Technology
Part Name
Description
View to exact match
A29800ATV-55F Datasheet PDF : 40 Pages
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Timing Waveforms for Alternate CE Controlled Write Operation
PA for program
555 for program SA for sector erase
2AA for erase 555 for chip erase
Data Polling
Addresses
PA
tWC
tAS
tWH
tAH
WE
OE
tCP
tWHWH1 or 2
CE
tWS
Data
tCPH
tDS
tDH
tBUSY
I/O7
tRH
RESET
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RY/BY
A29800A Series
DOUT
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Typ. (Note 1) Max. (Note 2)
Unit
Comments
Sector Erase Time
Chip Erase Time
0.3
1.5
sec Excludes 00h programming
4
16
sec prior to erasure
Byte Programming Time
6
100
μs
Word Programming Time
11
Chip Programming Time
Byte Mode
4
180
μs
Excludes system-level
16
sec overhead (Note 5)
(Note 3)
Word Mode
3
12
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(August, 2014, Version 1.3)
33
AMIC Technology, Corp.
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