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P80C31X2 View Datasheet(PDF) - NXP Semiconductors.

Part NameDescriptionManufacturer
P80C31X2 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) NXP
NXP Semiconductors. NXP
P80C31X2 Datasheet PDF : 62 Pages
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Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V ±10% OPERATION)
Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 5 V ±10%, VSS = 0 V1,2,3,4
Symbol Figure Parameter
Limits
16 MHz Clock
Unit
MIN
MAX
MIN
MAX
1/tCLCL 31
tLHLL
27
tAVLL
27
tLLAX
27
tLLIV
27
tLLPL
27
tPLPH
27
tPLIV
27
tPXIX
27
tPXIZ
27
tAVIV
27
tPLAZ
27
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
0
2 tCLCL–8
tCLCL –13
tCLCL –20
tCLCL –10
3 tCLCL –10
0
33
4 tCLCL –35
3 tCLCL –35
tCLCL –10
5 tCLCL –35
10
117
49.5
42.5
52.5
177.5
0
215
152.5
52.5
277.5
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRLRH
28
tWLWH
29
tRLDV
28
tRHDX
28
tRHDZ
28
tLLDV
28
tAVDV
28
tLLWL
28, 29
tAVWL
28, 29
tQVWX
29
tWHQX
29
tQVWH
29
tRLAZ
28
tWHLH
28, 29
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6 tCLCL –20
355
6 tCLCL –20
355
5 tCLCL –35
0
0
ns
ns
277.5
ns
ns
2 tCLCL –10
115
ns
8 tCLCL –35
465
ns
9 tCLCL –35
527.5
ns
3 tCLCL –15
3 tCLCL +15
172.5
202.5
ns
4 tCLCL –15
235
ns
tCLCL –25
37.5
ns
tCLCL –15
47.5
ns
7 tCLCL –5
432.5
ns
0
0
ns
tCLCL –10
tCLCL +10
52.5
72.5
ns
tCHCX
31
tCLCX
31
tCLCH
31
tCHCL
31
Shift register
High time
Low time
Rise time
Fall time
0.32 tCLCL
tCLCL – tCLCX
ns
0.32 tCLCL
tCLCL – tCHCX
ns
5
ns
5
ns
tXLXL
30
tQVXH
30
tXHQX
30
tXHDX
30
tXHDV
30
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
12 tCLCL
10 tCLCL –25 –
2 tCLCL –15
0
750
ns
600
ns
110
ns
0
ns
10 tCLCL –133 –
492
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
2003 Jan 24
40
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