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P80C31X2 View Datasheet(PDF) - NXP Semiconductors.

Part NameDescriptionManufacturer
P80C31X2 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) NXP
NXP Semiconductors. NXP
P80C31X2 Datasheet PDF : 62 Pages
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Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
IE
Address = 0A8H
Reset Value = 0X000000B
Bit Addressable
7
6
5
4
3
2
1
0
EA
ET2
ES
ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
Not implemented. Reserved for future use.
IE.5
ET2
Timer 2 interrupt enable bit.
IE.4
ES
Serial Port interrupt enable bit.
IE.3
ET1
Timer 1 interrupt enable bit.
IE.2
EX1
External interrupt 1 enable bit.
IE.1
ET0
Timer 0 interrupt enable bit.
IE.0
EX0
External interrupt 0 enable bit.
SU01522
Figure 22. Interrupt Enable (IE) Register
IP
Address = 0B8H
Bit Addressable
7
6
5
4
3
2
1
PT2
PS
PT1 PX1 PT0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
SYMBOL FUNCTION
IP.7
Not implemented, reserved for future use.
IP.6
Not implemented, reserved for future use.
IP.5
PT2
Timer 2 interrupt priority bit.
IP.4
PS
Serial Port interrupt priority bit.
IP.3
PT1
Timer 1 interrupt priority bit.
IP.2
PX1
External interrupt 1 priority bit.
IP.1
PT0
Timer 0 interrupt priority bit.
IP.0
PX0
External interrupt 0 priority bit.
Figure 23. Interrupt Priority (IP) Register
Reset Value = xx000000B
0
PX0
SU01523
IPH
Address = B7H
Reset Value = xx000000B
Bit Addressable
7
6
5
4
3
2
1
0
— PT2H PSH PT1H PX1H PT0H PX0H
BIT
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
SYMBOL
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
SU01524
Figure 24. Interrupt Priority HIGH (IPH) Register
2003 Jan 24
34
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