T-8208-BAL-DT View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

View to exact match

T-8208-BAL-DT

CelXpres™ ATM Interconnect

Agere -> LSI Corporation 

Advance Data Sheet

September 2001

CelXpres T8208

ATM Interconnect

List of Tables

Table

Page

Table 1. UTOPIA Pins .............................................................................................................................................. 14

Table 2. Shared UTOPIA Pins .................................................................................................................................. 15

Table 3. Cell Bus Pins .............................................................................................................................................. 16

Table 4. SDRAM Interface Pins ................................................................................................................................ 17

Table 5. Microprocessor Interface Pins .................................................................................................................... 18

Table 6. Translation SRAM Interface ......................................................................................................................... 19

Table 7. JTAG Pins ................................................................................................................................................... 19

Table 8. General-Purpose Pins ................................................................................................................................ 20

Table 9. Power Pins .................................................................................................................................................. 20

Table 10. Loop Filter Register Settings ..................................................................................................................... 24

Table 11. Access Times ........................................................................................................................................... 27

Table 12. Active and Ignore Truth Table .................................................................................................................. 33

Table 13. VPI Value Truth Table .............................................................................................................................. 34

Table 14. OAM Routing Control Truth Table ............................................................................................................ 34

Table 15. F5 Translation Record Addresses Table—8-Byte Records ....................................................................... 35

Table 16. F5 Translation Record Addresses Table—Extended Mode ...................................................................... 41

Table 17. Pin Configuration for 8-Bit UTOPIA .......................................................................................................... 53

Table 18. Pin Configuration for 16-Bit UTOPIA ........................................................................................................ 57

Table 19. Supported Memory Configurations ........................................................................................................... 71

Table 20. Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode ............ 74

Table 21. Queue Organization and Port Group Address/Priority Bits for 64 Ports in 8-Bit UTOPIA Mode and

32 Ports in 16-Bit UTOPIA Mode .............................................................................................................. 77

Table 22. Instruction Register ................................................................................................................................... 84

Table 23. Boundary-Scan Register Descriptions ...................................................................................................... 85

Table 24. Register Map .............................................................................................................................................. 88

Table 25. Identification 0 (IDNT0) (00h) ................................................................................................................... 92

Table 26. Identification 1 (IDNT1) (01h) .................................................................................................................... 92

Table 27. Identification 2 (IDNT2) (02h) ................................................................................................................... 92

Table 28. Direct Configuration/Control Register (DCCR) (28h)................................................................................ 93

Table 29. Interrupt Service Request (ISREQ) (29h) ................................................................................................. 94

Table 30. mclk PLL Configuration 0 (MPLLCF0) (2Ah) ............................................................................................ 94

Table 31. mclk PLL Configuration 1 (MPLLCF1) (2Bh) ............................................................................................ 95

Table 32. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) .................................................................................... 95

Table 33. GTL+ Control (GTLCNTRL) (2Fh) ........................................................................................................... 96

Table 34. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h) ................................................................ 97

Table 35. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h) ................................................................ 97

Table 36. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h) ................................................................ 97

Table 37. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h) ................................................................ 97

Table 38. Extended Memory Access (Little Endian) (EMA_LE) (34h) ....................................................................... 97

Table 39. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) ................................................................. 98

Table 40. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) ................................................................ 98

Table 41. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h) .................................................................. 99

Table 42. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h) .................................................................. 99

Table 43. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h) .................................................................. 99

Table 44. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h) .................................................................. 99

Table 45. Extended Memory Access (Big Endian) (EMA_BE) (34h) ....................................................................... 100

Table 46. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) ................................................................ 100

Table 47. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) ................................................................. 100

Table 48. GPIO Output Enable (GPIO_OE) (39h) ................................................................................................... 101

Table 49. GPIO Output Value (GPIO_OV) (3Bh) .................................................................................................... 101

Table 50. GPIO Input Value (GPIO_IV) (3Dh) ......................................................................................................... 101

Agere Systems Inc.

5

Share Link: