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T-8208-BAL-DB View Datasheet(PDF) - Agere -> LSI Corporation

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Description
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T-8208-BAL-DB
Agere
Agere -> LSI Corporation Agere
T-8208-BAL-DB Datasheet PDF : 214 Pages
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Advance Data Sheet
September 2001
CelXpres T8208
ATM Interconnect
9 UTOPIA Interface (continued)
In UTOPIA receive mode, the master controls the UTOPIA bus, and the slave only monitors the bus. Both master
and slave receive all cells and use their individual look-up tables to determine which cells are destined for their cell
bus. The master controls the enable (u_rxenb[3:0]) and address (u_rxaddr[4:0]) signals to the UTOPIA bus. The
slave monitors these signals to determine when the cell starts and which port is sending the cell.
In shared UTOPIA mode, the master always drives the u_rxaddr[4:0], u_txaddr[4:0], u_txsoc, u_rxenb*[3:0], and
u_txenb*[3:0] signals. These signals become high impedance on the slave when the slave_en bit in the main con-
figuration/control register (address 0110h) is set. Both the master and slave drive the u_txprty and u_txdata[7:0]
signals when they transmit a cell; therefore, these signals must go high impedance when not active. Clear the
tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) to force the u_txprty and u_txdata[7:0] sig-
nals to a high-impedance state when inactive.
U_TXCLK
U_TXENB*
U_TXSOC
U_TXDATA[7:0] P44 P45 P46 P47
X H0 H1 H2
P46 P47
U_TXPRTY
X
GRANT[0]
QS[6] QS[4] QS[2] QS[0] R[0]
GRANT[1]
QS[5] QS[3] QS[1] VALID
REQUEST[0]
INVALID
QR0 QR4 QR8
INVALID
REQUEST[1]
INVALID
QR1 QR5 QR9
INVALID
REQUEST[2]
INVALID
QR2 QR6 QR10
INVALID
REQUEST[3]
INVALID
QR3 QR7 QR11
Figure 11. TX UTOPIA Bus Sharing for 8-Bit UTOPIA Mode
INVALID
5-7786bF
Agere Systems Inc.
51
 

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