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T-8208-BAL-DB View Datasheet(PDF) - Agere -> LSI Corporation

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Description
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T-8208-BAL-DB
Agere
Agere -> LSI Corporation Agere
T-8208-BAL-DB Datasheet PDF : 214 Pages
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CelXpres T8208
ATM Interconnect
Advance Data Sheet
September 2001
Table of Contents (continued)
Contents
Page
19 Timing Requirements ..................................................................................................................................... 201
19.1 Microprocessor Interface Timing .......................................................................................................... 202
19.2 UTOPIA Timing .................................................................................................................................... 208
19.3 External LUT Memory Timing............................................................................................................... 209
19.4 Cell Bus Timing .................................................................................................................................... 211
19.5 SDRAM Interface Timing...................................................................................................................... 212
20 Outline Diagram ............................................................................................................................................. 213
21 Ordering Information ...................................................................................................................................... 214
List of Figures
Figure
Page
Figure 1. Functional Block Diagram ....................................................................................................................... 10
Figure 2. Dual Bus Implementation ........................................................................................................................ 11
Figure 3. 272-Pin PBGA—Top View ...................................................................................................................... 21
Figure 4. Translation RAM Memory Map—8-Byte Records ................................................................................... 31
Figure 5. Translation Record Types—8-Byte Records........................................................................................... 32
Figure 6. Translation RAM Flow Diagram .............................................................................................................. 37
Figure 7. Translation Record Types—Extended Mode .......................................................................................... 39
Figure 8. Translation RAM Memory Map—Extended Mode................................................................................... 40
Figure 9. Queue Priority Multiplexing ..................................................................................................................... 48
Figure 10. TX UTOPIA Cell Handling ..................................................................................................................... 49
Figure 11. TX UTOPIA Bus Sharing for 8-Bit UTOPIA Mode ................................................................................. 51
Figure 12. TX UTOPIA Bus Sharing for 16-Bit UTOPIA Mode ................................................................................52
Figure 13. Cell Bus Frame Format (Bit Positions for 16-User Mode) ..................................................................... 61
Figure 14. Cell Bus Frame Format (Bit Positions for 32-User Mode) ..................................................................... 62
Figure 15. Cell Bus Routing Headers ..................................................................................................................... 64
Figure 16. GTL+ External Circuitry ......................................................................................................................... 68
Figure 17. SDRAM Timing Parameters .................................................................................................................. 72
Figure 18. Crystal ................................................................................................................................................. 199
Figure 19. Negative Resistance Plot .................................................................................................................... 199
Figure 20. Nonmultiplexed Intel Mode Write Access Timing ................................................................................ 202
Figure 21. Nonmultiplexed Intel Mode Read Access Timing................................................................................ 202
Figure 22. Motorola Mode Write Access Timing................................................................................................... 204
Figure 23. Motorola Mode Read Access Timing .................................................................................................. 204
Figure 24. Multiplexed Intel Mode Write Access Timing....................................................................................... 206
Figure 25. Multiplexed Intel Mode Read Access Timing ...................................................................................... 206
Figure 26. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 209
Figure 27. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 209
Figure 28. Cell Bus Timing ................................................................................................................................... 211
Figure 29. SDRAM Interface Timing..................................................................................................................... 212
4
Agere Systems Inc.
 

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