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T-8208-BAL-DT View Datasheet(PDF) - Agere -> LSI Corporation

Part Name
Description
View to exact match
T-8208-BAL-DT
Agere
Agere -> LSI Corporation Agere
T-8208-BAL-DT Datasheet PDF : 214 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CelXpres T8208
ATM Interconnect
1 Product Overview (continued)
Advance Data Sheet
September 2001
ONE OR TWO
32K TO 256K x 8
(LUT) SRAMs
RX
UTOPIA
MICROPROCESSOR
TX
UTOPIA
RX
UTOPIA
INTERFACE
LOOK-UP
ENGINE
RX UTOPIA
FIFO
(4 CELLS)
RX PHY
FIFO
(16 CELLS)
MICROPROCESSOR
INTERFACE
CONTROL CELL
TX FIFO
(1 CELL)
CELL BUS
OUTPUT FIFO
(4 CELLS)
LOOPBACK
FIFO
(1 CELL)
CONTROL CELL
RX FIFO
(16 CELLS)
TX
UTOPIA
INTERFACE
TX UTOPIA
CELL BUFFER
(256 CELLS)
TX PHY
FIFO
(256 CELLS)
SDRAM
INTERFACE
CELL BUS
INPUT FIFO
(4 CELLS)
1M TO 16M x 16
SDRAM
Figure 1. Functional Block Diagram
CELL BUS
ARBITER
CELL BUS
INTERFACE
CELL BUS
MONITORING
CELL BUS
5-7542d F
10
Agere Systems Inc.
 

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