datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

TSA5059 View Datasheet(PDF) - Philips Electronics

Part Name
Description
View to exact match
TSA5059 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
Preliminary specification
TSA5059
Table 2 Explanation of Table 1
BIT
DESCRIPTION
MA1 and MA0 programmable address bits; see Table 3
A
N16 to N0
acknowledge bit
programmable main divider ratio control bits; N = N16 × 216 + N15 × 215 + ... + N1 × 21 + N0
PE
prescaler enable (prescaler by 2 is active when bit PE = 1)
R3 to R0
programmable reference divider ratio control bits; see Table 8
C1 and C0
charge pump current select bits; see Table 9
XCE
XT/COMP enable; XT/COMP output active when bit XCE = 1; see Table 10
XCS
XT/COMP select; signal select when bit XCE = 1, test mode enable when bit XCE = 0; see Table 10
T2, T1 and T0 test mode select when bit XCE = 0 and bit XCS = 1; see Table 10
P3, P2 and P1 Port P3, P2 and P1 output states
P0
Port P0 output state, except in test mode; see Table 10
Address selection (see Table 3)
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having
up to 4 synthesizers in one system. The relationship between MA1 and MA0 and the input voltage at pin AS is given in
Table 3.
Table 3 Address selection
MA1
0
0
1
1
MA0
0
1
0
1
VOLTAGE APPLIED TO PIN AS
0 to 0.1VCC
open-circuit
0.4VCC to 0.6VCC; note 1
0.9VCC to VCC
Note
1. This address is selected by connecting a 15 kresistor between pin AS and pin VCC.
Status at Power-On Reset (POR)
At power-on or when the supply voltage drops below approximately 2.75 V, internal registers are set according to
Table 4.
Table 4 Status at Power-on reset; note 1
BYTE DESCRIPTION
MSB
1 address
1
1
0
0
0
2 programmable divider 0
X
X
X
X
3 programmable divider X
X
X
X
X
4 control data
5 control data
1
X
X
X
X
0
0
0
1
X(2)
Notes
1. X = don’t care.
2. At Power-on reset, all output ports are in high-impedance state.
MA1
X
X
X
1(2)
MA0
X
X
X
X(2)
LSB
0
X
X
X
X(2)
CONTROL BIT
A
A
A
A
A
1999 Oct 05
7
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]