|AZ10/100LVEL33L||ECL/PECL ÷4 Divider|
Arizona Microtek, Inc
|AZ10/100LVEL33L Datasheet PDF : 10 Pages |
ARIZONA MICROTEK, INC.
ECL/PECL Differential Receiver with Variable Output Swing
• Silicon-Germanium for High Speed
• 150ps Typical Propagation Delay
• AZ100EP16VS Functionally Equivalent
to ON Semiconductor MC100EP16VS
• Available in a 3x3mm MLP Package
• S-Parameter (.s2p) and IBIS Model Files
available on Arizona Microtek Website
PART NUMBER MARKING NOTES
MLP 16 (3x3)
MLP 16 (3x3)
RoHS Compliant / AZ10/100EP16VSL+ 16S
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
2 Date code format: “Y” or “YY” for year followed by “WW” for week.
3 Date code “YWW” or “YYWW” on underside of part.
The AZ10/100EP16VS is a Silicon–Germanium (SiGe) differential receiver with variable output swing. The
EP16VS has functionality and output transition times similar to the EP16, with an input that controls the amplitude
of the Q/Q¯ outputs.
Connecting the BOOST pin to VEE increases the output swing by about 15% above standard ECL/PECL levels.
The BOOST pin is internally tied to VEE for the SOIC 8 and TSSOP 8 packages, and is under external user control
for the MLP 16 package. When both the BOOST pin and the VCTRL pin are not connected, the part operates with the
standard ECL/PECL output and VBB levels of the AZ10/100EP16 device. To ensure best performance, the BOOST
pin should be tied to VEE when the variable swing feature is used.
The operational range of the EP16VS control input, VCTRL, is from VREF (full swing) to VCC (min. swing).
Maximum swing is achieved by leaving the VCTRL pin open or tied to VEE. Simple control of the output swing can be
obtained by a variable resistor between the VREF and VCC pins, with the wiper driving VCTRL. Typical application
circuits and results are described in this Data Sheet.
The EP16VS provides a VREF (VBB/VREF) output for a DC bias when AC coupling to the device. The VREF pin
should be used only as a bias for the EP16VS as its current sink/source capability is limited. Whenever used, the
VREF pin should be bypassed to ground via a 0.01μF capacitor.
Under open input conditions for D/D¯ , the Q/Q¯ outputs are not guaranteed.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
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