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MC14013BFEL-2000 View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
MC14013BFEL(2000) Dual Type D Flip-Flop ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC14013BFEL Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each flip–flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip–flops for counter and toggle applications.
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4013B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5
V
(DC or Transient)
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8–Second Soldering)
– 55 to +125
°C
– 65 to +150
°C
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
MARKING
DIAGRAMS
14
MC14013BCP
AWLYYWW
1
14
14013B
AWLYWW
1
TSSOP–14
DT SUFFIX
CASE 948G
14
14
013B
ALYW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14013B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14013BCP
PDIP–14
2000/Box
MC14013BD
SOIC–14
55/Rail
MC14013BDR2 SOIC–14 2500/Tape & Reel
MC14013BDT
TSSOP–14
96/Rail
MC14013BDTR2 TSSOP–14 2500/Tape & Reel
MC14013BF
SOEIAJ–14 See Note 1.
MC14013BFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14013B/D
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