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CS8130_97 View Datasheet(PDF) - Cirrus Logic

Part NameDescriptionManufacturer
CS8130_97 CS8130 Revision G Addendum Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS8130_97 Datasheet PDF : 4 Pages
1 2 3 4
CS8130 Revision G Addendum
Multi-Standard Infrared Transceiver (DS134PP2, JUN ‘97)
The following items represent permanent changes to the specification of the CS8130 IR transceiver.
1) The Silicon Revision Register (Register 28) reads 0010, indicating rev G silicon.
2) The default receive sensitivity setting is changed to 00011 (Register 6 resets to 0011).
3) Oscillator low power mode is now the default condition after reset (Register 21 resets to 0100).
4) The BLKR bit (Register 4, bit D2) blocks the RXD output data during those periods when the transmit
LEDs are on. This prevents the UART/system reading the transmitted data. The re-enable signal for
the receiver is delayed by 8 µs from when the LEDs are turned off. Set to 1 to block RXD data, set to
0 to allow RXD data through during transmission. This bit goes to 0 upon RESET.
5) An additional control bit was added which causes the CS8130 receiver to ignore the falling edge of the
IR pulse. This bit is called ENPOS, and it is bit D2 of Register #7. ENPOS is normally 1, which causes
the falling edge to be ignored. This results in greater range in IrDA and high-frequency ASK (Sharp
500 kHz) modes. ENPOS should be set to 0 for low-frequency amplitude modulated modes.
6) For IrDA/HP-SIR pulse width modes, two additional control bits have been added:
a. The THIN bit (Register 7, bit D1) allows the minimum acceptable pulse width to be reduced from
1 µs to 0.5 µs when set to 1. This bit has effect only when the receiver is programmed to mode 1a
(fixed 1.6 µs pulses only) or 1c (receive 1.6 µs to 3/16 of a bit cell pulses). This bit resets to 0.
b. The WIDE bit (Register 1, Bit D2) expands the maximum allowable pulse width to 9/16 of a bit
cell when set to 1. This bit has effect only when the receiver is set to mode 1a (fixed 1.6 µs pulses
For normal IrDA operation, it is recommended that THIN be set to 0 and WIDE be set to 1. Under these
conditions, the qualification boundaries for receiver mode 1c (receive 1.6 µs to 3/16 of a bit cell pulses)
are identical to the qualification boundaries for receiver mode 1a (fixed 1.6 µs pulses only). This bit
resets to 1.
7) A TV remote receive mode hesitate bit has been added (Register 1, Bit D3). When this bit is set to 0,
the RXD pin will remain high until the first valid IR signal is detected. At that time, the RXD pin will
output serial data at the specified baud rate until the receiver is disabled (Register 0, bit D1). If this bit
is set to 1, the RXD pin will immediately and continuously output data. This bit resets to 0.
8) The ASK transmit carrier frequency formula has changed:
MD=(3.6864E6/FR)-2 , where MD is the Modulator Divider Value and FR is the desired modulation
frequency (Registers 10 & 11). The RESET default value for MD is now 5, yielding a default carrier
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
NOV ‘97
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