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LC72131 View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
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LC72131
SANYO
SANYO -> Panasonic SANYO
LC72131 Datasheet PDF : 23 Pages
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LC72131, 72131M
Continued from preceding page.
No.
Control block/data
DO pin control data
DOC0, DOC1, DOC2
Functions
• Data that determines the DO pin output
DOC2
0
0
0
0
1
1
1
1
DOC1
0
0
1
1
0
0
1
1
DOC0
0
1
0
1
0
1
0
1
DO pin state
Open
Low when the unlock state is detected
end-UC*1
Open
Open
The IO1 pin state*2
The IO2 pin state*2
Open
The open state is selected after the power-on reset.
Note: 1. end-UC: Check for IF counter measurement completion
(6)
Related data
UL0, UL1,
CTE,
IOC1, IOC2
Unlock detection data
UL0, UL1
(7)
Phase comparator
control data
DZ0, DZ1
(8)
ΠWhen end-UC is set and the IF counter is started (i.e., when CTE is changed
from zero to one), the DO pin automatically goes to the open state.
 When the IF counter measurement completes, the DO pin goes low to indicate
the measurement completion state.
Ž Depending on serial data I/O (CE: high) the DO pin goes to the open state.
2. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high)
will output the contents of the internal DO serial data in synchronization with the
CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2).
• Selects the phase error (øE) detection width for checking PLL lock.
A phase error in excess of the specified detection width is seen as an unlocked state.
UL1
UL0
øE detection width
Detector output
0
0 Stopped
Open
0
10
øE is output directly
1
0 ±0.55 µs
øE is extended by 1 to 2 ms
1
1 ±1.11 µs
øE is extended by 1 to 2 ms
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data
becomes zero.
• Controls the phase comparator dead zone.
DOC0,
DOC1,
DOC2
DZ1
DZ0
0
0 DZA
0
1 DZB
1
0 DZC
1
1 DZD
Dead zone mode
Dead zone widths: DZA < DZB < DZC < DZD
Clock time base
(9) TBC
Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output
from the BO1 pin. (BO1 data is invalid in this mode.)
BO1
Charge pump control data • Forcibly controls the charge pump output.
DLC
DLC
Charge pump output
0
Normal operation
(10)
1
Forced low
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to
low and setting Vtune to VCC. (This is the deadlock clearing circuit.)
Continued on next page.
No. 4921-11/23
 

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