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74ABT125D/AUJ View Datasheet(PDF) - NXP Semiconductors.

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Description
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74ABT125D/AUJ
NXP
NXP Semiconductors. NXP
74ABT125D/AUJ Datasheet PDF : 15 Pages
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Nexperia
74ABT125
Quad buffer; 3-state
9,
QHJDWLYH
SXOVH

9
9,
SRVLWLYH
SXOVH
9

90

WI
WU

90
W:

90

WU
WI

90

W:
DDL
9,
*
9&&
92
'87
57
a. Input pulse definition
b. Test circuit
Fig 8.
Test data is given in Table 8.
Test circuit definitions:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Test circuit for measuring switching times
9(;7
5/
&/
5/
PQD
Table 8.
Input
VI
3.0 V
Test data
fI
1 MHz
tW
500 ns
tr, tf
2.5 ns
Load
CL
50 pF
RL
500
VEXT
tPHL, tPLH
open
tPZH, tPHZ
open
tPZL, tPLZ
7.0 V
74ABT125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 25 November 2015
© Nexperia B.V. 2017. All rights reserved
7 of 15
 

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