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FDS6812A View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
FDS6812A Datasheet PDF : 5 Pages
1 2 3 4 5
November 2001
FDS6812A
Dual N-Channel Logic Level PWM Optimized PowerTrench® MOSFET
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
6.7 A, 20 V.
RDS(ON) = 22 m@ VGS = 4.5 V
RDS(ON) = 35 m@ VGS = 2.5 V
Low gate charge (12 nC typical)
High performance trench technology for extremely
low RDS(ON)
High power and current handling capability
DD1
DD1
DD2
DD2
SO-8
Pin 1 SO-8
SS2GS2SS1GG1
5
4
6
Q1
3
7
2
Q2
8
1
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDS6812A
FDS6812A
13’’
Ratings
20
± 12
6.7
35
2
1.6
1
0.9
–55 to +150
78
40
Tape width
12mm
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
2500 units
©2001 Fairchild Semiconductor Corporation
FDS6812A Rev B (W)
 

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