HD74LS138FPEL_05 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
View to exact match
HD74LS138FPEL_05 Datasheet PDF : 8 Pages
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HD74LS138
3-Line-to-8-Line Decoders / Demultiplexers
REJ03D0434–0300
Rev.3.00
Jul.13.2005
The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three
enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS138P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74LS138FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
FP
(FP-16DAV)
HD74LS138RPEL SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
-
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Pin Arrangement
Select
Inputs
A1
B2
C3
G2A 4
Enable G2B 5
Inputs
G1 6
Outputs Y7 7
GND 8
A
B
Y0
C
Y1
G2A
Y2
G2B
Y3
G1
Y4
Y7
Y5
Y6
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3 Outputs
11 Y4
10 Y5
9 Y6
(Top view)
Rev.3.00, Jul.13.2005, page 1 of 7
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