Micrel, Inc.
KSZ8765CLX
Tail Tagging Mode
The tail tag is only seen and used by the Port 5 interface, which should be connected to a processor by the SW5-GMII,
RGMII, MII, or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on Port 5. Only bits
[3:0] are used for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting
Register 12 bit [1].
Figure 12. Tail Tag Frame Format
Table 14. Tail Tag Rules
Ingress to Port 5 (Host to KSZ8765CLX)
Bits [3:0]
Destination
0,0,0,0
Reserved
0,0,0,1
Port 1 (direct forward to Port 1)
0,0,1,0
Port 2 (direct forward to Port 2)
0,1,0,0
Port 3 (direct forward to Port 3)
1,0,0,0
Port 4 (direct forward to Port 4)
1,1,1,1
Port 1, 2, 3, and 4 (direct forward to Port 1, 2, 3,4)
Bits [7:4]
0,0,0,0
Queue 0 is used at destination port
0,0,0,1
Queue 1 is used at destination port
0,0,1,0
Queue 2 is used at destination port
0,0,1,1
Queue 3 is used at destination port
0, 1,x,x
Anyhow send packets to specified port in bits [3:0]
1, x,x,x
Bits [6:0] will be ignored as normal (address look-up)
Egress from Port 5 (KSZ8765CLX to Host)
Bits [1:0]
Source
0,0
Port 1 (packets from Port 1)
0,1
Port 2 (packets from Port 2)
1,0
Port 3 (packets from Port 3)
1,1
Port 4 (packets from Port 4)
July 23, 2014
47
Revision 1.0