KSZ8765CLXCC View Datasheet(PDF) - Micrel
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KSZ8765CLXCC Datasheet PDF : 153 Pages
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Micrel, Inc.
KSZ8765CLX
In external mode, when using an external 50MHz clock source as SW5-RMII reference clock, the KSZ8765CLX Port 5
should be set to normal mode by the strap pin LED2_1 or the port Register 86 bit 7. The normal mode of the
KSZ8765CLX device will start to work when it receives the 50MHz reference clock on the TXC5/REFCLKI5 pin from an
external 50MHz clock source.
Table 11. Port 5 SW5-RMII Connection(6)
MAC-to-MAC Connection
KSZ8765CLX SW5-RMII PHY Mode
MAC-to-PHY Connection
KSZ8765CLX SW5-RMII MAC Mode
External
MAC
SW5-RMII
Signals
Type
Description
External
PHY
SW5-RMII
Signals
Type
REF_CLKI
RXC5
Output 50MHz
in Clock Mode
Reference Clock
50MHz
REFCLKI5
Input 50MHz in
Normal Mode
CRS_DV
RXDV5/CRSDV5
Output
Carrier
Sense/Receive
Data Valid
CRS_DV
TXEN5
Input
Receive Error
RXER
TXER5
Input
RXD[1:0]
RXD5[1:0]
Output
Receive Data
Bit[1:0]
RXD[1:0]
TXD5[1:0]
Input
TX_EN
TXEN5
Input
Transmit Data
Enable
TX_EN
RXDV5/CRSDV5
Output
TXD[1:0]
TXD5[1:0]
Input
Transmit Data
Bit 1
TXD[1:0]
RXD5[1:0]
Output
50MHz
REFCLKI5
Input 50MHz in
Clock Mode
Reference Clock
REF_CLKI
RXC5
Output 50MHz
in Clock Mode
Note:
6. MAC/PHY mode in RMII is different from MAC/PHY mode in MII. There is no strap pin and register configuration request in RMII; just follow the
singal connections in the table above.
Functional Overview: Advanced Functionality
QoS Priority Support
The KSZ8765CLX provides quality of service (QoS) for applications such as VoIP and video conferencing. The
KSZ8765CLX offers one, two, or four priority queues per port by setting the Port Control 13 Registers bit [1] and the Port
Control 0 Registers bit [0]. The 1/2/4 queues split as follows.
[Port Control 9 Registers bit [1], Control 0 bit [0]] = 00 Single output queue as default.
[Port Control 9 Registers bit [1], Control 0 bit [0]] = 01 Egress port can be split into two priority transmit queues.
[Port Control 9 Registers bit [1], Control 0 bit [0]] = 10 Egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8765CLX. Queue 3 is the highest priority queue and Queue 0
is the lowest priority queue. The Port Control 9 Registers bit [1] and the Port Control 0 Registers bit [0] are used to enable
split transmit queues for Ports 1, 2, 3, 4, and 5, respectively. If a port's transmit queue is not split, high priority and low
priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or to use programmable weighted fair
queuing for the four priority queue scale by the Port Control 14, 15, 16, and 17 Registers (default values are 8, 4, 2, 1 by
their bits [6:0].
Register 130 bit [7:6] Prio_2Q[1:0] is used when the two-queue configuration is selected. These bits are used to map the
2-bit result of IEEE 802.1p from Registers 128 and 129 or TOS/DiffServ mapping from Registers 144-159 (for four
queues) into two-queue mode with priority high or low.
Please see the descriptions of Register 130 bits [7:6] for more detail.
July 23, 2014
43
Revision 1.0
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