KSZ8765CLXCC View Datasheet(PDF) - Micrel

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Description

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KSZ8765CLXCC

Integrated 5-Port 10/100 Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

Micrel 

Micrel, Inc.

KSZ8765CLX

Port 5 GMAC5 SW5-GMII Interface

The table below shows two connection methods. The first is an external GMAC connecting in SW5-GMII GPHY mode.

The second is an external GPHY connecting in SW5-GMII GMAC mode. The MAC mode or PHY mode setting is

determined by the strap Pin 62 LED2_1.

Table 8. Port 5 SW5-GMII Connection

GMAC-to-GMAC Connection

KSZ8765CLX GMAC5 SW5-GMII GPHY Mode

External

GMAC

SW5-GMII

Signals

Type

MRXDV

TXEN5

Input

MRXER

TXER5

Input

MRXD[7:0]

TXD5[7:0]

Input

MGRXC

GTXC5

Input

MCOL

COL5

Output

MCRS

CRS5

Output

MRXEN

RXDV5

Output

MTXER

RXER5

Output

MRXD[7:0]

RXD5[3:0]

Output

MGRXC

GRXC5

Output

Description

Transmit Enable

Transmit Error

Transmit Data

Bit[3:0]

Transmit Clock

Collision

Detection

Carrier Sense

Receive Data

Valid

Receive Error

Receive Data

Bit[3:0]

Receive Clock

GMAC-to-GPHY Connection

KSZ8765CLX GMAC5 SW5-GMII GMAC Mode

External

GPHY

SW5-GMII

Signals

Type

MTXEN

RXDV5

Output

MTXER

RXER5

Output

MTXD[7:0]

RXD5[7:0]

Output

MGTXC

GRXC5

Output

MCOL

COL5

Input

MCRS

CRS5

Input

MRXDV

TXEN5

Input

MRXER

TXER5

Input

MRXD[7:0]

TXD5[7:0]

Input

MGRXC

GTXC5

Input

The Port 5 GMAC5 SW5-GMII interface operates at up to 1Gbps. In 1Gbps mode, GMII supports the full-duplex only. The

GMII interface is 8-bits of data in each direction. Additional signals on the transmit side indicate when data is valid or

when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and

without physical layer errors. For half-duplex operation in 10/100Mbps mode, there is a COL signal that indicates a

collision has occurred during transmission.

Port 5 GMAC5 SW5-RGMII Interface

The table below shows the RGMII reduced connections when connecting to an external GMAC or GPHY.

Table 9. Port 5 SW5-RGMII Connection

KSZ8765CLX SW5-RGMII Connection

External GMAC/GPHY

SW5-RGMII Signals

MRX_CTL

TXD5_CTL

MRXD[3:0]

TXD5[3:0]

MRX_CLK

GTX5_CLK

MTX_CTL

RXD5_CTL

MTXD[3:0]

RXD5[3:0]

MGTX_CLK

GRXC5

Type

Input

Input

Input

Output

Output

Output

Description

Transmit Control

Transmit Data Bit[3:0]

Transmit Clock

Receive Control

Receive Data Bit[3:0]

Receive Clock

July 23, 2014

41

Revision 1.0

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