KSZ8765CLX-EVAL View Datasheet(PDF) - Micrel
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KSZ8765CLX-EVAL Datasheet PDF : 153 Pages
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Micrel, Inc.
KSZ8765CLX
Functional Overview: Power
The KSZ8765CLX device requires 3.3V analog power. An external 1.2V LDO provides the necessary 1.2V to power the
analog and digital logic cores. The various I/Os can be operated at 1.8V, 2.5V, and 3.3V. The table below illustrates the
various voltage options and requirements of the device.
Power Signal Name
VDDAT
VDDIO
VDD12A
VDD12D
GNDA
GNDD
Device Pin
2,12,76
34,48,70
1
26, 42, 73
3, 21, 78
27, 33, 47, 61, 71
Requirement
3.3V input power to the analog blocks of transceiver in the device.
Choice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input power pins power
the I/O circuitry of the device.
1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V to power the
internal analog and digital cores.
Analog ground.
Digital ground.
Functional Overview: Power Management
The KSZ8765CLX supports enhanced power management in a low power state, with energy detection to ensure low
power dissipation during device idle periods. There are three operation modes under the power management function
which are controlled by the Register 14 bits [4:3] and the Port Control 10 Register bit [3] as shown below:
Register 14 bits [4:3] = 00 normal operation mode
Register 14 bits [4:3] = 01 energy detect mode
Register 14 bits [4:3] = 10 soft power-down mode
Register 14 bits [4:3] = 11 reserved
The Port Control 10 Register 29, 45, 61, 77 bit [3] = 1 are for the port-based power-down mode.
Table 2 indicates all internal function block statuses under four different power management operation modes.
Table 2. Internal Function Block Status
KSZ8765CLX
Function Blocks
Internal PLL Clock
TX/RX PHY
MAC
Host Interface
Normal Mode
Enabled
Enabled
Enabled
Enabled
Power Management Operation Modes
Energy Detect Mode
Soft Power-Down Mode
Disabled
Disabled
Energy detect at RX
Disabled
Disabled
Disabled
Disabled
Disabled
Normal Operation Mode
This is the default setting bits [4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8765CLX is in
normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is ready for CPU read or
write.
During normal operation mode, the host CPU can set the bits [4:3] in Register 14 to change the current normal operation
mode to any one of the other three power management operation modes.
Energy Detect Mode
Energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8765CLX port is not connected to an active link partner. In this mode, the device will save more power when the
July 23, 2014
30
Revision 1.0
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