KSZ8765CLX-EVAL View Datasheet(PDF) - Micrel

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KSZ8765CLX-EVAL

Integrated 5-Port 10/100 Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

Micrel 

Micrel, Inc.

KSZ8765CLX

Introduction

The KSZ8765CLX contains four 10/100 physical layer transceivers, four media access control (MAC) units, and one

Gigabit media access control (GMAC) units with an integrated Layer 2-managed switch. The device runs in two modes.

The first mode is as a four-port standalone switch. The second is as a five-port switch where the fifth port is provided

through a Gigabit media independent interface that supports GMII, RGMII, MII, and RMII. This is useful for implementing

an integrated broadband router.

The KSZ8765CLX has the flexibility to reside in a managed mode. In a managed mode, a host processor has complete

control of the KSZ8765CLX via the SPI bus or the MDC/MDIO interface.

On the media side, the KSZ8765CLX supports IEEE 802.3 100Base-FX on Port 1 and Port 2 fiber ports and 10/100BASE-

T/TX on Port 3 and Port 4 copper ports with Auto-MDI/MDI-X. The KSZ8765CLX can be used as a fully managed five-port

switch or hooked up to a microprocessor via its SW-GMII/RGMII/MII/RMII interfaces to allow for integrating into a variety

of environments.

Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP

technology that makes the design more efficient, allows for reduced power consumption, and smaller die size.

Major enhancements from the KSZ8995FQ and KS8895FMQ to the KSZ8765CLX include more host interface options

such as the GMII and RGMII interfaces, power saving features such as IEEE 802.1az energy-efficient Ethernet (EEE),

MLD snooping, wake-on-LAN (WoL), port-based ACL filtering for port security, enhanced QoS priority, rapid spanning

tree, IGMP snooping, port mirroring support, and flexible rate limiting.

Functional Overview: Physical Layer (PHY)

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI

conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII

data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding

followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3

current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1 transformer ratio. It has a typical

rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing

jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving

side starts with the equalization filter to compensate for intersymbol interference (ISI) over the twisted pair cable. Since

the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its

characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This

is an ongoing process and can self-adjust against environmental changes such as temperature variations.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to

compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit

converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used

to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.

PLL Clock Synthesizer

The KSZ8765CLX generates 125MHz, 83MHz, 41MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are

generated from an external 25MHz crystal or oscillator.

July 23, 2014

20

Revision 1.0

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