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MC14011BFELG View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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MC14011BFELG
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC14011BFELG Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
TL
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
VESD ESD Withstand Voltage
V
Human Body Model
> 3000
Machine Model
> 300
Charged Device Model
N/A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
MARKING DIAGRAMS
14
140xxBG
AWLYWW
1
SOIC−14
14
14
0xxB
ALYWG
G
1
TSSOP−14
xx
A
WL, L
YY, Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
DEVICE INFORMATION
Device
MC14001B
MC14011B
MC14023B
Description
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Triple 3−Input NAND Gate
MC14025B
MC14071B
MC14073B
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
MC14081B
MC14082B
Quad 2−Input AND Gate
Dual 4−Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 11
Publication Order Number:
MC14001B/D
 

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