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ADW71205YSTZ View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADW71205YSTZ
ADI
Analog Devices ADI
ADW71205YSTZ Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD2S1205
Parameter
Degradation of Signal (DOS)
Sin/Cos Threshold
Angular Accuracy (Worst Case)
Angular Latency (Worst Case)
Time Latency
Sin/Cos Mismatch
Min Typ Max Unit
4.0 4.09 4.2 V p-p
33 Degrees
66 Degrees
125 μs
385 420 mV
Loss of Tracking (LOT)
Tracking Threshold
5
Degrees
Time Latency
1.1 ms
Hysteresis
4
Degrees
VOLTAGE REFERENCE
REFOUT
2.39 2.47 2.52 V
Drift
70
ppm/°C
PSRR
−60
dB
CHARGE-PUMP OUTPUT (CPO)
Frequency
204.8
kHz
Duty Cycle
50
%
POWER SUPPLY
IDD Dynamic
20 mA
ELECTRICAL CHARACTERISTICS
VIL, Voltage Input Low
0.8 V
VIH, Voltage Input High
2.0
V
VOL, Voltage Output Low
0.4 V
VOH, Voltage Output High
4.0
V
IIL, Low Level Input Current
−10
(Non-Pull-Up)
+10 μA
IIL, Low Level Input Current (Pull-Up) −80
+80 μA
IIH, High Level Input Current
−10
+10 μA
IOZH, High Level Three-State Leakage −10
+10 μA
IOZL, Low Level Three-State Leakage −10
+10 μA
Conditions/Comments
DOS goes low when Sin or Cos exceeds threshold
DOS indicated before angular output error exceeds limit
Maximum electrical rotation before DOS is indicated
DOS latched low when Sin/Cos amplitude mismatch
exceeds threshold
LOT goes low when internal error signal exceeds
threshold; guaranteed by design
Guaranteed by design
±IOUT = 100 μA
Square wave output, CLKIN = 8.192 MHz
+1 mA load
−1 mA load
SAMPLE, CS, RDVEL, CLKIN, SOE pins
RD, FS1, FS2, RESET pins
1 The voltages for Sin, SinLO, Cos, and CosLO relative to AGND must be between 0.2 V and AVDD.
Rev. A | Page 4 of 20
 

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