CLKIN
SAMPLE
CS
RD
RDVEL
SO
fCLKIN
t1
t2
t1
t3
t3
t5
t5
t4
t6
POSITION
t4
t6
t7
t7
VELOCITY
AD2S1205
RD
SCLK
SO
t8
tSCLK
MSB
t9
t10
MSB – 1
LSB
RDVEL DOS
Figure 8. Serial Port Read Timing
Table 7. Serial Port Timing1
Parameter
Description
t8
MSB read time RD/CS to SCLK
t9
SO enable time RD/CS to DB valid
t10
Data access time, SCLK to DB valid
t11
Bus relinquish time RD/CS to SO high-Z
tSCLK
Serial clock period (25 MHz maximum)
1 t1 to t7 are as defined in Table 6.
t11
LOT
PAR
Min
Typ
15
40
Max
tSCLK
30
30
18
Unit
ns
ns
ns
ns
ns
Rev. A | Page 15 of 20