ADW71205WSTZ View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADW71205WSTZ Datasheet PDF : 20 Pages
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CS Input
The device is enabled when CS is held low.
RDVEL Input
RDVEL input is used to select between the angular position
register and the angular velocity register, as shown in Figure 7.
RDVEL is held high to select the angular position register and
low to select the angular velocity register. The RDVEL pin must
be set (stable) at least t4 before the RD pin is pulled low.
AD2S1205
RD Input
The 12-bit data bus lines are normally in a high impedance
state. The output buffer is enabled when CS and RD are held
low. A falling edge of the RD signal transfers data to the output
buffer. The selected data is made available to the bus to be read
within t6 of the RD pin going low. The data pins return to a high
impedance state when the RD pin returns to a high state within
t7. When reading data continuously, wait a minimum of t3 after
RD is released before reapplying it.
CLKIN
fCLKIN
t1
t1
SAMPLE
t2
CS
t3
t3
RD
RDVEL
t5
t4
t5
t4
DATA
DON'T CARE
POSITION
t7
t6
t6
Figure 7. Parallel Port Read Timing
VELOCITY
t7
Table 6. Parallel Port Timing
Parameter
Description
fCLKIN
Frequency of clock input
t1
SAMPLE pulse width
t2
Delay from SAMPLE before RD/CS low
t3
RD pulse width
t4
Set time RDVEL before RD/CS low
t5
Hold time RDVEL after RD/CS low
t6
Enable delay RD/CS low to data valid
t7
Disable delay RD/CS low to data high-Z
Min
6.144
2 × (1/fCLKIN) + 20
6 × (1/fCLKIN) + 20
18
5
7
Typ
8.192
Max
10.24
30
18
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 13 of 20
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