W25Q32FWTBIQ View Datasheet(PDF) - Winbond

Part Name

Description

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W25Q32FWTBIQ

1.8V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

Winbond 

W25Q32FW

During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high,

the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC

Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit

cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter

and operate in the QPI mode.

Refer to section 7.1 for Status Register descriptions.

/CS

Mode 3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3

CLK Mode 0

Mode 0

DI

(IO0)

Instruction

(01h/31h/11h)

Register-1/2/3 in

76543210

*

DO

(IO1)

* = MSB

High Impedance

Figure 9a. Write Status Register-1/2/3 Instruction (SPI Mode)

/CS

CLK

IO0

Mode 3

Mode 0

0123

Instruction SR1/2/3

01/31/11h in

40

Mode 3

Mode 0

IO1

51

IO2

62

IO3

73

Figure 9b. Write Status Register-1/2/3 Instruction (QPI Mode)

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Publication Release Date: July 01, 2016

- Revision H

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