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W25Q32FWTBIQ View Datasheet(PDF) - Winbond

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W25Q32FWTBIQ Datasheet PDF : 94 Pages
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W25Q32FW
S15 S14 S13 S12 S11 S10 S9 S8
SUSPEND STATUS
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BITS
(non-volatile OTP)
RESERVED
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
(non-volatile)
SUS CMP LB3 LB2 LB1 (R) QE SRP1
Figure 4b. Status Register-2
7.1.8 Erase/Program Suspend Status (SUS) Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
7.1.9 Security Register Lock Bits (LB[3:1]) Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
7.1.10 Quad Enable (QE) Volatile/Non-Volatile Writable
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state ((factory default for part numbers with ordering
options “IG” and “IF”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory default for
Quad Enabled part numbers with ordering option “IQ”), the Quad IO2 and IO3 pins are enabled, and /WP
and /HOLD functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,
QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a
“1” to a “0”.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard
SPI or Dual SPI operation, the QE bit should never be set to a 1.
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