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W25Q32FWTBIQ View Datasheet(PDF) - Winbond

Part NameW25Q32FWTBIQ Winbond
Winbond Winbond
Description1.8V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
W25Q32FWTBIQ Datasheet PDF : 94 Pages
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W25Q32FW
7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q32FW. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device
is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,
Erase/Program Suspend status, output driver strength, and power-up. The Write Status Register instruction
can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks,
Hold/Reset functions, and output driver strength. Write access to the Status Register is controlled by the state
of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during
Standard/Dual SPI operations, the /WP pin.
7.1 Status Registers
S7 S6 S5 S4 S3 S2 S1 S0
Status Register Protect 0
(Volatile/Non-Volatile Writable)
Sector Protect Bit
(Volatile/Non-Volatile Writable)
Top/Bottom Protect Bit
(Volatile/Non-Volatile Writable)
Block Protect Bits
(Volatile/Non-Volatile Writable)
Write Enable Latch
(Status-Only)
Erase/Write In Progress
(Status-Only)
SRP0 SEC TB BP2 BP1 BP0 WEL BUSY
Figure 4a. Status Register-1
7.1.1 Erase/Write In Progress (BUSY) Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE
in AC Characteristics). When the program, erase or write status/security register instruction has completed,
the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2 Write Enable Latch (WEL) Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
7.1.3 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The factory
default setting for the Block Protection Bits is 0, none of the array protected.
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GENERAL DESCRIPTIONS
The W25Q32FW (32M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 1.65V to 1.95V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving packages.
The W25Q32FW array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32FW has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)

FEATURES
● New Family of SpiFlash Memories
   – W25Q32FW: 32M-bit / 4M-byte
   – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
   – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
   – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
   – QPI: CLK, /CS, IO0, IO1, IO2, IO3
   – Software & Hardware Reset
● Highest Performance Serial Flash
   – 104MHz Single, Dual/Quad SPI clocks
   – 208/416MHz equivalent Dual/Quad SPI
   – 50MB/S continuous data transfer rate
   – Min 100K Program-Erase cycles per secto
   – More than 20-year data retention
● Efficient “Continuous Read” and QPI Mode
   – Continuous Read with 8/16/32/64-Byte Wrap
   – As few as 8 clocks to address memory
   – Quad Peripheral Interface (QPI) reduces instruction overhead
   – Allows true XIP (execute in place) operation
   – Outperforms X16 Parallel Flash
● Flexible Architecture with 4KB sectors
   – Uniform Sector/Block Erase (4K/32K/64K-Byte)
   – Program 1 to 256 byte per programmable page
   – Erase/Program Suspend & Resume
● Advanced Security Features
   – Software and Hardware Write-Protect
   – Power Supply Lock-Down and OTP protection
   – Top/Bottom, Complement array protection
   – Individual Block/Sector array protection
   – 64-Bit Unique ID for each device
   – Discoverable Parameters (SFDP) Register
   – 3X256-Bytes Security Registers with OTP locks
   – Volatile & Non-volatile Status Register Bits
● Space Efficient Packaging
   – 8-pin SOIC/VSOP 208-mil, XSON 4x4-mm
   – 8-pad WSON 6x5-mm / 8x6-mm
   – 16-pin SOIC 300-mil (additional /RESET)
   – 24-ball TFBGA 8x6-mm(additional /RESET)
   – 12-ball WLCSP
   – Contact Winbond for KGD and other options

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