W25Q32FWTBIQ View Datasheet(PDF) - Winbond

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Description

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W25Q32FWTBIQ

1.8V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

Winbond 

W25Q32FW

6. FUNCTIONAL DESCRIPTIONS

6.1 SPI / QPI Operations

Power Up

Device Initialization

& Status Register Refresh

(Non-Volatile Cells)

Hardware

Reset

Hardware

Reset

Standard SPI

Dual SPI

Quad SPI

Enable QPI (38h)

Disable QPI (FFh)

QPI

SPI Reset

(66h + 99h)

QPI Reset

(66h + 99h)

Figure 3. W25Q32FW Serial Flash Memory Operation Diagram

6.1.1 Standard SPI Instructions

The W25Q32FW is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI

input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO

output pin is used to read data or status from the device on the falling edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not

being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising

edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.1.2 Dual SPI Instructions

The W25Q32FW supports Dual SPI operation when using instructions such as “Fast Read Dual Output

(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device

at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for

quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical

code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become

bidirectional I/O pins: IO0 and IO1.

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