datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

W25Q32FWTBIQ View Datasheet(PDF) - Winbond

Part NameW25Q32FWTBIQ Winbond
Winbond Winbond
Description1.8V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
W25Q32FWTBIQ Datasheet PDF : 94 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
W25Q32FW
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 57).
If needed a pull-up resistor on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q32FW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data
or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When
QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware
protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin
function is not available since this pin is used for IO2. See Figure 1a-d for the pin configuration of Quad I/O
operation.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful
when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of
Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3.
See Figure 1a-d for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.6 Reset (/RESET)
The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3
pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting.
When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC
and TFBGA package, a dedicated /RESET pin is provided and it is independent of QE bit setting.
-9-
Direct download click here
 

GENERAL DESCRIPTIONS
The W25Q32FW (32M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 1.65V to 1.95V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving packages.
The W25Q32FW array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32FW has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)

FEATURES
● New Family of SpiFlash Memories
   – W25Q32FW: 32M-bit / 4M-byte
   – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
   – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
   – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
   – QPI: CLK, /CS, IO0, IO1, IO2, IO3
   – Software & Hardware Reset
● Highest Performance Serial Flash
   – 104MHz Single, Dual/Quad SPI clocks
   – 208/416MHz equivalent Dual/Quad SPI
   – 50MB/S continuous data transfer rate
   – Min 100K Program-Erase cycles per secto
   – More than 20-year data retention
● Efficient “Continuous Read” and QPI Mode
   – Continuous Read with 8/16/32/64-Byte Wrap
   – As few as 8 clocks to address memory
   – Quad Peripheral Interface (QPI) reduces instruction overhead
   – Allows true XIP (execute in place) operation
   – Outperforms X16 Parallel Flash
● Flexible Architecture with 4KB sectors
   – Uniform Sector/Block Erase (4K/32K/64K-Byte)
   – Program 1 to 256 byte per programmable page
   – Erase/Program Suspend & Resume
● Advanced Security Features
   – Software and Hardware Write-Protect
   – Power Supply Lock-Down and OTP protection
   – Top/Bottom, Complement array protection
   – Individual Block/Sector array protection
   – 64-Bit Unique ID for each device
   – Discoverable Parameters (SFDP) Register
   – 3X256-Bytes Security Registers with OTP locks
   – Volatile & Non-volatile Status Register Bits
● Space Efficient Packaging
   – 8-pin SOIC/VSOP 208-mil, XSON 4x4-mm
   – 8-pad WSON 6x5-mm / 8x6-mm
   – 16-pin SOIC 300-mil (additional /RESET)
   – 24-ball TFBGA 8x6-mm(additional /RESET)
   – 12-ball WLCSP
   – Contact Winbond for KGD and other options

Share Link : Winbond
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]