LC7442, 7442E
Clamp Pulse
• A/D converter clamp
Since clamp pulses are output with the timing shown in the figure below, it is setup to fall within the pedestal range.
On reset and during standby, the KH signal goes to a positive polarity, and is output as such.
A/D input
Notes: 1: The conditions t3 > 0 µs and t4 > 0.5 µs must be met.
2: The value of 4.8 µs for t1 is the value when registers CLPAJ0 and 1 are 00.
• D/A converter clamp
D/A output
Digital data in the A region:
Y D/A:
R-Y D/A:
B-Y D/A:
MSB
LSB
000000
100000
100000
Clamping is applied by the main screen horizontal synchronization signal.
External Control Output Timing
• Relationship with the LC7480 A/D converter
Sampling data
(LC7480 output)
Note: Since this circuit operates at the high speeds shown in this figure, care is required to keep leads as short as possible in the wiring used in this circuit.
No. 4412-20/22