LC78681KE-L View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
View to exact match
LC78681KE-L Datasheet PDF : 24 Pages
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LC78681KE, 78681KE-L
Continued from preceding page.
No.
Name
50
WRQ
51
RWC
52
SQOUT
53
COIN
54
CQCK
55
RES
56
M/L
57
LASER
58
16M
59
4.2M
60
CONT
61
TEST5
62
CS
63
XIN
64
XOUT
I/O
Description
O
I
WRQ goes high when the subcode Q data passes the CRC check. An external controller can read out data from
SQOUT by monitoring this pin and applying a CQCK signal. Set M/L to low when data is required LSB first.
O
The control microprocessor can send commands to the LC78681KE by setting RWC high and then sending command
I
data synchronized with CQCK.
I
I
This pin must be set low briefly after power is first applied.
I
Similar to pins number 50, 51, 52, 53 and 54 described above.
O Output pin controllable by serial data sent from the microprocessor.
O 16.9344 MHz output pin
O 4.2336 MHz output pin
O Output pin controllable by serial data sent from the microprocessor.
I
LSI test pin. Normally left open.
I
Chip select pin. The LC78681KE becomes active when this pin is low. (A pull-down resistor is built-in.)
I
Connections for a 16.9344 MHz crystal oscillator
O
Pin Applications
1. HF signal input circuit; Pin 8: EFMIN, pin 7: EFMO, pin 6: EFMO
An EFM signal (NRZ) with an optimal slice level can be acquired by inputting the HF signal to EFMIN.
2. PLL clock generation circuit; Pin 4: PDO, Pin 3: AI, Pin 2: AO
A VCO can be constructed by combining the LC78681KE with the Sanyo LA9210. The PDO pin swings in the
positive direction when the VCO phase lags.
No. 4969-7/24
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