|LC78681KE-L||Digital Signal Processor for Compact Disc Players|
SANYO -> Panasonic
|LC78681KE-L Datasheet PDF : 24 Pages |
9. Error flag output; Pin 45: EFLG, pin 49: FSX
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal.
The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined
from the extent of the high level that appears here.
10. Subcode P, Q, and R to W output circuit; Pin 46: PW, pin 44: SBSY, pin 47: SFSY, pin 48: SBCK
PW is the subcode signal output pin, and all the codes P, Q, and R to W can be read out by sending eight clocks to
the SBCK pin within 136 µs after the fall of SFSY. The signal that appears on the PW pin changes on the falling
edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output
for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode
symbol (P to W). Subcode data P is output on the fall of this signal.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The
fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode
block. (EIAJ format)
11. Subcode Q output circuit; Pin 50: WRQ, pin 51: RWC, pin 52: SQOUT, pin 54: CQCK, pin 56: M/L, pin 62: CS
RES = low
Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin.
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